Solid-state image pickup device, method of fabricating the same, and camera module

ABSTRACT

According to one embodiment, a solid-state image pickup device includes a pixel array that includes a two-dimensionally arranged matrix of photoelectric conversion lements corresponding to pixels of a picked-up image. Each of the photoelectric conversion elements includes a first conductive semiconductor region and a second conductive semiconductor region between which an uneven junction plane is formed.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a division of and claims the benefit of priorityunder 35 U.S.C. §119 from U.S. Ser. No. 14/093,632 filed Dec. 2, 2013,and claims the benefit of priority under 35 U.S.C. §120 from JapanesePatent Application No. 2013-135122 filed Jun. 27, 2013; the entirecontents of each of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a solid-state imagepickup device, a method of fabricating the solid-state image pickupdevice, and a camera module.

BACKGROUND

In the related art, an electronic device such as a digital camera or amobile terminal with camera function is provided with a camera moduleincluding a solid-state image pickup device. The solid-state imagepickup device includes a plurality of photoelectric conversion elementsarranged two-dimensionally corresponding to each pixel of a picked-upimage. Each of the photoelectric conversion elements photoelectricallyconverts incident light into a quantity of electric charges (forexample, electrons) corresponding to a light-received quantity toaccumulate as information indicating luminance of each pixel.

In such solid-state image pickup device, miniaturization of thephotoelectric conversion element has proceeded with downsizing of thedevice. As the miniaturization of the photoelectric conversion elementproceeds, since the number of electrons to be accumulated by each of thephotoelectric conversion elements, so-called the number of saturatedelectrons becomes less, reproduction characteristic of the picked-upimage is reduced. In solid-state image pickup device, therefore, thephotoelectric conversion element capable of increasing the number ofsaturated electrons in a limited region is desired.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a schematic configuration of adigital camera provided with a solid-state image pickup device accordingto a first embodiment;

FIG. 2 is a block diagram illustrating a schematic configuration of thesolid-state image pickup device according to the first embodiment;

FIG. 3 is an explanatory diagram of a photoelectric conversion elementin cross-sectional view according to the first embodiment;

FIG. 4 is an explanatory diagram of the photoelectric conversion elementin plan view according to the first embodiment;

FIG. 5 is an explanatory diagram of a light-receiving surface in aphotoelectric conversion element in plan view according to a firstmodified example;

FIG. 6 is an explanatory diagram of a light-receiving surface in aphotoelectric conversion element in plan view according to a secondmodified example;

FIGS. 7A to 7D are explanatory diagrams illustrating forming processesof the photoelectric conversion element according to the firstembodiment;

FIG. 8 is an explanatory diagram of a photoelectric conversion elementin cross-sectional view according to a second embodiment;

FIG. 9 is an explanatory diagram of a photoelectric conversion elementin cross-sectional view according to a third embodiment;

FIG. 10 is an explanatory diagram of a photoelectric conversion elementin cross-sectional view according to a fourth embodiment;

FIG. 11 is an explanatory diagram of a photoelectric conversion elementin cross-sectional view according to a fifth embodiment.

DETAILED DESCRIPTION

In general, according to one embodiment, a solid-state image pickupdevice includes a pixel array that includes a two-dimensionally arrangedmatrix of photoelectric conversion elements corresponding to pixels of apicked-up image. Each of the photoelectric conversion elements includesa first conductive semiconductor region and a second conductivesemiconductor region between which an uneven junction plane is formed.

Exemplary embodiments of a solid-state image pickup device, a method offabricating the solid-state image pickup device, and a camera modulewill be explained below in detail with reference to the accompanyingdrawings. The present invention is not limited to the followingembodiments.

First Embodiment

FIG. 1 is a block diagram illustrating a schematic configuration of adigital camera 1 provided with a solid-state image pickup device 14according to a first embodiment. As illustrated in FIG. 1, the digitalcamera 1 includes a camera module 11 and a post-processing unit 12.

The camera module 11 includes an image pickup optical system 13 and thesolid-state image pickup device 14. The image pickup optical system 13receives light from an object to form an object image. The solid-stateimage pickup device 14 picks up the object image formed by the imagepickup optical system 13 and outputs an image signal obtained by theimage pickup to the post-processing unit 12. Such camera module 11 isapplied to, for example, an electronic device such as a mobile terminalwith camera in addition to the digital camera 1.

The post-processing unit 12 includes an ISP (Image Signal Processor) 15,a storage unit 16, and a display unit 17. The ISP 15 carries out asignal processing of the image signal input from the solid-state imagepickup device 4. The ISP 15 carries out a high-quality pictureprocessing such as, for example, a noise removal processing, a deadpixel correction processing, and a resolution conversion processing.

Further, the ISP 15 outputs the image signal after the signal processingto the storage unit 16, the display unit 17 and a signal processingcircuit 21 (see FIG. 2), which will be described later, provided in thesolid-state image pickup device 14 within the camera module 11. Theimage signal fed back to the camera module 11 from the ISP 15 is usedfor adjustment or control of the solid-state image pickup device 14.

The storage unit 16 stores the image signal input from the ISP 15 as animage. In addition, the storage unit 16 outputs the image signal of thestored image to the display unit 17 depending on an operation of a user.The display unit 17 displays the image depending on the image signalinput from the ISP 15 or the storage unit 16. Such display unit 17 is,for example, a liquid crystal display.

The solid-state image pickup device 14 provided in the camera module 11will be described below with reference to FIG. 2. FIG. 2 is a blockdiagram illustrating a schematic configuration of the solid-state imagepickup device 14 according to the first embodiment. As illustrated inFIG. 2, the solid-state image pickup device 14 includes an image sensor20 and a signal processing circuit 21.

Here, the image sensor 20 which is a so-called back-illuminated CMOS(Complementary Metal Oxide Semiconductor) image sensor will bedescribed. In the CMOS image sensor, a wiring layer is formed on asurface opposite to a surface of the photoelectric conversion elementwhich incident light enters, the photoelectric conversion elementphotoelectrically converting the incident light.

Further, the image sensor 20 according to the present embodiment is notlimited to the back-illuminated CMOS image sensor, but may be arbitraryimage sensors such as a front-illuminated CMOS image sensor or CCD(Charge Coupled Device) image sensor.

The image sensor 20 includes a peripheral circuit 22 and a pixel array23. In addition, the peripheral circuit 22 includes a vertical shiftregister 24, a timing control unit 25, a CDS (correlated double samplingunit) 26, an ADC (analog/digital converting unit) 27, and a line memory28.

The pixel array 23 is provided in an image pickup region of the imagesensor 20. In the pixel array 23, a plurality of photoelectricconversion elements corresponding to each pixel of the picked-up imageare disposed in a form of two-dimensional array (matrix form) in ahorizontal direction (row direction) and a vertical direction (columndirection). Then, the pixel array 23 accumulates signal charges (forexample, electrons) generated depending on the quantity of the incidentlight by each of the photoelectric conversion elements corresponding toeach pixel.

The timing control unit 25 is a processing unit that outputs a pulsesignal acting as a reference of operation timing with respect to thevertical shift register 24. The vertical shift register 24 is aprocessing unit that outputs a selection signal to the pixel array 23,the selection signal being used to sequentially select the photoelectricconversion element which reads the signal charge out of the plurality ofphotoelectric conversion elements disposed in the form of array(matrix), by the row.

The pixel array 23 outputs the signal charge accumulated in each of thephotoelectric conversion elements, which is selected through theselection signal input from the vertical shift register 24 by the row,to the CDS 26 from the photoelectric conversion element, as the pixelsignal indicating the luminance of each pixel.

The CDS 26 is a processing unit that removes a noise from the pixelsignal input from the pixel array 23 by the correlated double samplingand then outputs it to the ADC 27. The ADC 27 is a processing unit thatconverts an analog pixel signal input from the CDS 26 to a digital pixelsignal and then outputs it to the line memory 28. The line memory 28 isa processing unit that temporarily holds the pixel signal input from theADC 27 and outputs it the signal processing circuit 21 for each row ofthe photoelectric conversion element in the pixel array 23.

The signal processing circuit 21 is a processing unit that performs apredetermined signal processing on the pixel signal input from the linememory 28 and outputs it the post-processing unit 12. The signalprocessing circuit 21 performs the signal processing such as, forexample, lens shading correction, flaw correction, and noise reductionprocessing on the pixel signal.

Like this, in the image sensor 20, the plurality of photoelectricconversion elements disposed in the pixel array 23 photoelectricallyconvert the incident light into the signal charge of the quantitycorresponding to the light-received quantity and accumulates theconverted signal charge, and the peripheral circuit 22 reads the signalcharge accumulated in each of the photoelectric conversion elements asthe pixel signal, thus performing the image pickup.

Each of the photoelectric conversion elements disposed in the pixelarray 23 of the image sensor 20 is a photodiode which is formed by PNjunction between a first conductive-type (herein, referred to as an“N-type”) semiconductor (herein, referred to as a “Si: silicon”) regionand a second conductive-type (herein, referred to as a “P-type”) Siregion.

Then, the photoelectric conversion element accumulates the signal charge(herein, “electron”), which is generated by photoelectrically convertingthe incident light, in the junction portion between the N-type Si regionand the P-type Si region. Therefore, as the area of the junction planebetween the N-type Si region and the P-type Si region is large, thenumber of accumulable electrons (hereinafter, referred to as “the numberof saturated electrons”) of the photoelectric conversion elementincreases.

However, as miniaturization of the photoelectric conversion elementproceeds with downsizing of the solid-state image pickup device 14,since the area of the junction plane between the N-type Si region andthe P-type Si region is reduced in each of the photoelectric conversionelements, the number of saturated electrons of each photoelectricconversion element becomes less and thus reproduction characteristics ofthe picked-up image decreases.

In the solid-state image pickup device 14 according to the firstembodiment, therefore, each of the photoelectric conversion elements isconfigured to increase the number of saturated electrons within thelimited region. A configuration of the photoelectric conversion elementaccording to the first embodiment will be described below with referenceto FIGS. 3 and 4.

FIG. 3 is an explanatory diagram of a photoelectric conversion element 3in cross-sectional view according to the first embodiment, and FIG. 4 isan explanatory diagram of the photoelectric conversion element 3 in planview according to the first embodiment. Further, FIG. 4 illustratesschematically a cross section of the photoelectric conversion element 3corresponding to one pixel of the picked-up image taken along adirection perpendicular to a light receiving surface. In addition, FIG.4 illustrates schematically the light receiving surface of thephotoelectric conversion element 3 corresponding to one pixel of thepicked-up image.

As illustrated in FIG. 3, the photoelectric conversion element 3includes an N-type Si region 4 provided on a semiconductor substrate 31such as a Si wafer and a first P-type Si region 5 provided on an upperface and a lateral face of the N-type Si region 4. Further, a ShallowTrench Isolation (STI) 32 is formed at an outer side more than the firstP-type Si region 5 provided on the lateral face of the N-type Si region4. Each of the photoelectric conversion elements 3 is electricallyisolated from an adjacent other photoelectric conversion element 3 bythe STI 32.

Furthermore, the photoelectric conversion element 3 includes a pluralityof second P-type Si regions 51 provided so as to protrude toward theN-type Si region 4 from the junction plane between the first P-type Siregion 5 provided at the upper face portion of the N-type Si region 4and the N-type Si region 4.

As illustrated in FIG. 4, the second P-type Si regions 51 are providedso as to be in the form of stripe in plan view, and the second P-type Siregions 51 are provided so as to be parallel with each other and beparallel with the light-receiving surface of the photoelectricconversion element 3. Further, hereinafter, in a case of aiming a P-typesemiconductor region formed by the first P-type Si region 5 and thesecond P-type Si regions 51, it is simply referred to as “P-type Siregion”.

Thus, the photoelectric conversion element 3 includes the second P-typeSi regions 51 protruding in a depth direction toward the N-type Siregion 4 from the first P-type Si region 5, in addition to the firstP-type Si region 5. For this reason, in the photoelectric conversionelement 3, the PN junction is formed at the junction portion between theN-type Si region 4 and the first P-type Si region 5 and the PN junctionis also formed at the junction portion between the N-type Si region 4and the second P-type Si regions 51.

In the photoelectric conversion element 3, that is, as illustrated by athick line in FIG. 3, the junction plane between the N-type Si region 4and the P-type Si region has a concave/convex shape which are formedwith a convex portion 5 a protruding toward the semiconductor substrate31 and a concave portion 5 b concaved toward the light-receiving surfaceof the photoelectric conversion element 3. Therefore, according to thephotoelectric conversion element 3, since the area of the junction planebetween the N-type Si region 4 and the P-type Si region, that is, thearea of the PN junction is enlarged compared to another photoelectricconversion element not provided with the second P-type Si region 51, itis possible to increase the number of saturated electrons.

Further, the present embodiment is described on the case provided sothat the second P-type Si regions 51 are parallel with each other asviewed from plane and are parallel with the light-receiving surface ofthe photoelectric conversion element 3, but the shape of the secondP-type Si regions 51 as viewed from plane is not limited thereto.

Modified examples of the second P-type Si regions 51 according to thefirst embodiment will be described below with reference to FIGS. 5 and6. FIG. 5 is an explanatory diagram of a light-receiving surface in aphotoelectric conversion element 3 a according to a first modifiedexample as viewed from plane, and FIG. 6 is an explanatory diagram of alight-receiving surface in a photoelectric conversion element 3 baccording to a second modified example as viewed from plane. Further, inFIGS. 5 and 6, the same components as in FIG. 3 are denoted by the samereference numerals as in FIG. 3.

As illustrated in FIG. 5, the photoelectric conversion element 3 aaccording to the first modified example includes a stripe-shaped secondP-type Si region 52 which is disposed in a lattice pattern as viewedfrom plan. Further, similar to the second P-type Si region 51illustrated in FIG. 3, the second P-type Si region 52 is also providedso as to protrude in the depth direction toward the N-type Si region 4from the first P-type Si region 5. Thus, since the area of the PNjunction is more enlarged, it is possible to further increase the numberof saturated electrons.

In addition, as illustrated in FIG. 6, the photoelectric conversionelement 3b according to the second modified example includes secondP-type Si regions 53 which are provided in a form of plural dots on thelight-receiving surface of the photoelectric conversion element 3 b.Further, similar to the second P-type Si region 51 illustrated in FIG.3, the second P-type Si region 53 is also provided so as to protrude inthe depth direction toward the N-type Si region 4 from the first P-typeSi region 5. Even by the second P-type Si regions 53, since the area ofthe PN junction is enlarged, it is possible to increase the number ofsaturated electrons.

A method of fabricating the solid-state image pickup device 14 providedwith the photoelectric conversion element 3 will be described below.Further, in a fabricating process of the solid-state image pickup device14, fabricating processes other than a forming process of thephotoelectric conversion element 3 are the same as in the solid-stateimage pickup device, in general. Therefore, the forming process of thephotoelectric conversion element 3 will be described herein, and thedescription of other fabricating processes will not be presented.

FIGS. 7A to 7D are explanatory diagrams illustrating the forming processof the photoelectric conversion element 3 according to the firstembodiment. In the process of forming the photoelectric conversionelement 3, first, as illustrated in FIG. 7A, the N-type Si region 4 isformed on the semiconductor substrate 31.

The N-type Si region 4 is formed by, for example, ion-implanting anN-type impurity such as phosphorus into the semiconductor substrate 31and then performing an annealing treatment. Further, the N-type Siregion 4 may be a Si layer doped with the N-type impurity, which isformed on the semiconductor substrate 31 by, for example, CVD (ChemicalVapor Deposition).

Thereafter, as illustrated in FIG. 7B, a trench (groove) is formed at aformation position of the STI 32 in the N-type Si region 4.Subsequently, as illustrated in FIG. 7C, the first P-type Si region 5and the STI 32 are sequentially formed.

The first P-type Si region 5 is formed by, for example, ion-implanting aP-type impurity such as boron into the upper face, the lateral face(lateral face of trench), and the bottom face of the N-type Si region 4and then performing the annealing treatment.

In addition, the STI 32 is formed by burying a silicon oxide in aninterior of the trench in which the first P-type Si region 5 is formedat an inner periphery, using the CVD, for example. Further, in a stateillustrated in FIG. 7C, the junction plane between the upper face of theN-type Si region 4 and the first P-type Si region 5 is a planar shape asillustrated by the thick line in FIG. 7C.

Subsequently, as illustrated in FIG. 7D, the second P-type Si region 51is formed. The second P-type Si region 51 is formed by, for example,forming a mask provided with a stripe-shaped opening on the upper faceof the first P-type Si region 5, ion-implanting the P-type impuritytoward the N-type Si region 4 over the mask, and then performing theannealing treatment.

Further, in a case of forming the second P-type Si region 51, a higherenergy is applied to the P-type impurity than in the case of forming thefirst P-type Si region 5 to perform the ion implantation. For thisreason, the ion implantation of the P-type impurity into the interior ofthe N-type Si region 4 is conducted deeper than that of the P-typeimpurity into the first P-type Si region 5, and then the second P-typeSi region 51 is formed so as to protrude in the depth direction towardthe N-type Si region 4 from the first P-type Si region 5 by theannealing treatment.

As a result, in a state illustrated in FIG. 7D, the junction planebetween the N-type Si region 4 and the P-type Si region is aconcave/convex shape as illustrated by the thick line in FIG. 7D. Here,as is apparent from a comparison between FIGS. 7C and 7D, the area ofthe PN junction (see thick line illustrated in FIGS. 7C and 7D) afterthe formation of the second P-type Si regions 51 is larger than thatbefore the formation of the second P-type Si regions 51.

Thus, in the forming process of the photoelectric conversion element 3,the second P-type Si region 51 is formed by ion-implanting the P-typeimpurity with energy higher than in the case of forming the first P-typeSi region 5 to form the PN junction of the concave/convex shape.

For this reason, according to the photoelectric conversion element 3,even when the second P-type Si regions 51 is provided, since the area ofthe PN junction can be enlarged to increase the number of saturatedelectrons, it is possible to improve the reproduction characteristics ofthe picked-up image.

Further, in the example illustrated in FIGS. 7A to 7D, the second P-typeSi region 51 is formed by the ion-implantation, but the second P-type Siregion 51 may be formed by methods other than the ion-implantation.

For example, after a structure illustrated in FIG. 7C is formed, theN-type Si region 4 and the first P-type Si region 5 are patterned in theshape as illustrated in FIG. 7D by performing a patterning using aphotolithography technique.

In this state, the region in which the second P-type Si region 51illustrated in FIG. 7D is formed is the striped groove as viewed fromplane. Then, the second P-type Si region 51 may be formed by burying Si,which is doped with the P-type impurity, in the groove by the CVD.

As described above, the photoelectric conversion element 3 according tothe first embodiment is formed so that the junction plane between theN-type Si region 4 and the P-type Si region is the convex/concave shape.Thus, since the number of saturated electrons of each photoelectricconversion element 3 is increased, it is possible to improve thereproduction characteristics of the picked-up image. Further, theconfigurations of the photoelectric conversion elements 3, 3a, and 3billustrated in FIGS. 3 to 6 are an example, and these configurations canvariously be modified. A photoelectric conversion element according toother embodiments will be described below.

Second Embodiment

FIG. 8 is an explanatory diagram of a photoelectric conversion element3c according to a second embodiment as viewed from cross section. Asillustrated in FIG. 8, the photoelectric conversion element 3c includesa first N-type Si region 41 which is formed more thinly than the N-typeSi region 4 and a second N-type Si region 42 which is formed more deeplythan the first N-type Si region 41, instead of the N-type Si region 4illustrated in FIG. 3.

Furthermore, the photoelectric conversion element 3c is configured inthe same manner as illustrated in FIG. 3, except that the first N-typeSi region 41 and the second N-type Si region 42 illustrated in FIG. 8are provided instead of the N-type Si region 4 illustrated in FIG. 3.For example, as viewed from plane, the second N-type Si region 42 may beformed in the parallel stripe shape as illustrated in FIG. 4, in thelattice pattern as illustrated in FIG. 5, and in the dot shape asillustrated in FIG. 6.

For example, the second N-type Si region 42 is formed by ion-implantingthe N-type impurity into the semiconductor substrate 31 with the energyhigher than in the case of forming the first N-type Si region 41.

For this reason, the second N-type Si region 42 is formed so as toprotrude toward the semiconductor substrate 31 from the junction planebetween the first N-type Si region 41 and the semiconductor substrate31. Furthermore, the second N-type Si region 42 may also be formed byburying Si doped with the N-type impurity in the groove, which is formedby patterning the first N-type Si region 41 and the semiconductorsubstrate 31, using the CVD rather than the ion implantation.

According to the second embodiment, as illustrated by the thick line inFIG. 8, since the junction plane between the first and second N-type Siregions 41 and 42 and the P-type Si region is the convex/concave shape,it is possible to increase the number of saturated electrons compared toa case where the second P-type Si region 51 is not provided.

Further, according to the second embodiment, in a case of not formingdeeply the first N-type Si region 41 for certain reasons, since thesecond N-type Si region 42 is provided to cover at least the secondP-type Si regions 51, it is possible to form the PN junction of theconvex/concave shape.

Third Embodiment

FIG. 9 is an explanatory diagram of a photoelectric conversion element3d according to a third embodiment as viewed from cross section. Asillustrated in FIG. 9, the photoelectric conversion element 3d isconfigured in the same manner as the photoelectric conversion element 3illustrated in FIG. 3, except that a third P-type Si region 54 isprovided inside the N-type Si region 4. The third P-type Si region 54 isformed by ion-implanting the P-type impurity into the N-type Si region 4with the energy higher than in the case of forming the second P-type Siregions 51.

According to the third embodiment, since the PN junction is also formedat an interface between the third P-type Si region 54 and the N-type Siregion 4 to accumulate the photoelectrically converted electron, it ispossible to further increase the number of saturated electrons.

Fourth Embodiment

FIG. 10 is an explanatory diagram of a photoelectric conversion element3 e according to a fourth embodiment as viewed from cross section. Asillustrated in FIG. 10, the photoelectric conversion element 3 eincludes a second N-type Si region 43 which is formed more deeply up toa deep position of the semiconductor substrate 31 than the second N-typeSi region 42 illustrated in FIG. 8.

In addition, the photoelectric conversion element 3 e includes a secondP-type Si region 55 which is provided inside the second N-type Si region43 and is formed more deeply up to the deep position of thesemiconductor substrate 31 than the second P-type Si region 51illustrated in FIG. 8. Further, the photoelectric conversion element 3 eincludes an insulation region 61 which is formed inside the secondP-type Si region 55 by an insulator such as Si oxide.

In the case of forming the photoelectric conversion element 3 e,firstly, the structure illustrated in FIG. 7C is formed by the processesillustrated in FIGS. 7A to 7C. Subsequently, the trench is formed towardthe depth direction in the semiconductor substrate 31 from predeterminedpositions of plural locations in the upper face of the first P-type Siregion 5. The trench formed by the above process may be formed in theparallel stripe shape as viewed from plane, in the lattice pattern asviewed from plane, and in the dot shape as viewed from plane.Furthermore, the trench is back-filled by Si oxide. Subsequently, thesecond N-type Si region 43 and the second P-type Si region 55 are formedby sequentially ion-implanting the N-type impurity and the P-typeimpurity into an inner periphery of the trench and then performing theannealing treatment. Finally, the insulation region 61 is formed byburying the insulator such as Si oxide inside the trench using, forexample, the CVD, and the photoelectric conversion element 3 eillustrated in FIG. 10 is formed.

Like this, according to the fourth embodiment, since the second N-typeSi region 43 and the second P-type Si region 55 are formed byion-implanting the N-type impurity and the P-type impurity into theinner periphery of the trench after the formation of the trench, the PNjunction is formed up to the deeper position of the semiconductorsubstrate 31.

Therefore, according to the fourth embodiment, since the PN junctionformed in the photoelectric conversion element 3 e further extendstoward the depth direction of the semiconductor substrate 31, it ispossible to further increase the number of saturated electrons.

Fifth Embodiment

FIG. 11 is an explanatory diagram of a photoelectric conversion element3 f according to a fifth embodiment as viewed from cross section. Asillustrated in FIG. 11, the photoelectric conversion element 3 f differsfrom that illustrated in FIG. 10 in that the second P-type Si region 55illustrated in FIG. 10 is not provided and a conductive region 62 isprovided in place of the insulation region 61. In addition, theconductive region 62 of the photoelectric conversion element 3 f isconnected to a DC power source 71 through a wiring 72, and a negativevoltage is applied to the conductive region 62 from the DC power source71.

The photoelectric conversion element 3 f is formed without using theprocess of forming the second P-type Si region 55 in the process offorming the photoelectric conversion element 3 e illustrated in FIG. 10and by burying a conductor such as a poly-Si in the trench using, forexample, the CVD, instead of the process of forming the insulationregion 61.

In the photoelectric conversion element 3 f, when the negative voltageis applied to the conductive region 62, an inversion region 56 in whichpositive and negative of electrical characteristics are inverted isformed at a portion which comes in contact with the conductive region 62in the second N-type Si region 43. The inversion region 56 has the samefunction as the second P-type Si regions 55 illustrated in FIG. 10.

Therefore, according to the fifth embodiment, even without using theprocess of forming the second P-type Si region 55 (FIG. 10), since thePN junction further extends toward the depth direction of thesemiconductor substrate 31 as in the fourth embodiment, it is possibleto much more increase the number of saturated electrons.

Further, a material of the conductive region 62 in the fifth embodimentis not limited to the poly-Si, but may be a transparent electrodematerial represented by, for example, ITO (Indium Tin Oxide). In thecase of using the transparent electrode material as the material of theconductive region 62, it is possible to increase the quantity ofsaturated electrons while suppressing the quantity of incident lightwhich enters the photoelectric conversion element 3 f.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A method of fabricating a solid-state imagepickup device including photoelectric conversion elements correspondingto pixels of a picked-up image, the method comprising: two-dimensionallyforming first conductive semiconductor regions on a semiconductorsubstrate in a matrix; and forming second conductive semiconductorregions corresponding to the respective first conductive semiconductorregions so that junction planes between the first conductivesemiconductor regions and the second conductive semiconductor regionsare uneven.
 2. The method of fabricating the solid-state image pickupdevice according to claim 1, wherein the second conductive semiconductorregion is formed so that the junction plane includes stripedconcave/convex portions in parallel with a light-receiving surface ofthe photoelectric conversion element.
 3. The method of fabricating thesolid-state image pickup device according to claim 2, wherein thestriped concave/convex portions are formed in a lattice pattern.
 4. Themethod of fabricating the solid-state image pickup device according toclaim 1, wherein the second conductive semiconductor region is formed sothat the junction plane includes dotted concave/convex portions.
 5. Themethod of fabricating the solid-state image pickup device according toclaim 1, wherein the second conductive semiconductor region is formed byproviding a first second-conductive region on a surface of a side whichlight enters in the first conductive semiconductor region and forming asecond second-conductive region that protrudes toward the firstconductive semiconductor region from a junction plane between the firstsecond-conductive region and the first conductive semiconductor region.6. The method of fabricating the solid-state image pickup deviceaccording to claim 5, wherein the first conductive semiconductor regionis formed by providing a first first-conductive region on asemiconductor substrate and forming a second first-conductive regionthat protrudes toward the semiconductor substrate from a junction planebetween the first first-conductive region and the semiconductorsubstrate.
 7. The method of fabricating the solid-state image pickupdevice according to claim 1, wherein a second conductive semiconductorregion is further formed inside the first conductive semiconductorregion.
 8. The method of fabricating the solid-state image pickup deviceaccording to claim 5, wherein a trench is formed toward an inside of thesecond region from a surface of a side of a second region, which lightenters, in the second conductive semiconductor region, and an insulationregion is formed inside the trench by an insulator.
 9. The method offabricating the solid-state image pickup device according to claim 5,wherein a trench is formed toward an inside of the second region from asurface of a side of a second region, which light enters, in the secondconductive semiconductor region, a conductive region is formed insidethe trench by a conductor, and a power supply that applies negativevoltage and the conductive region are connected to each other throughthe wiring.